By Sanjay Dabral, Timothy J. Maloney
The 1st accomplished consultant to ESD defense and I/O designBasic ESD and I/O layout is the 1st booklet dedicated to ESD (electrostatic discharge) defense and input/output layout. Addressing the growing to be call for in for high-speed I/O designs, it bridges the distance among ESD examine and present VLSI layout practices and gives a much-needed reference for practising engineers who're often referred to as upon to benefit the topic at the job.This quantity offers an built-in remedy of ESD, I/O, and procedure parameter interactions that either I/O designers and method designers can use. It examines key elements in I/O and ESD layout and trying out, and is helping the reader reflect on ESD and reliability matters up entrance while making I/O offerings. Emphasizing readability and ease, this publication specializes in layout rules that may be utilized greatly as this dynamic box maintains to conform. easy ESD and I/O layout: * Describes suggestions for design-oriented ESD defense * Explains format equipment that increase ESD safeguard designs * Addresses uncomplicated I/O designs, together with new difficulties corresponding to combined voltage interfaces * Discusses fabrication points affecting ESD and I/O safeguard * Illustrates recommendations utilizing various figures and examples * Expresses equipment physics when it comes to basic electric circuit types * Cross-references the fabric to plain texts within the fieldEssential for engineers in and an individual designing circuits, structures, or units for destiny applied sciences, easy ESD and I/O layout can be an invaluable reference for researchers and graduate scholars focused on middle VLSI layout or laptop structure.
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Extra info for Basic ESD and IO design
Consider an NMOS finger that has snapped back at VII and has a current of It! due to external applied voltage. Now the voltage in the drain region tries to decrease to a minimum point of Vsb at snapback. However, the external voltage (due to ESD) does not allow this to happen, as it is directly connected to the drain node, so to meet the external voltage, the current in this snapped·back finger has to increase. If the increased current cannot cause the drain voltage to decrease below Va (perhaps by discharging the external charged source), then the device passes into the second breakdown region.
This is done using a high-pass filter circuit consisting of a capacitor (C2 ) and a resistor (R 2 ) [Amerasekera 1995, p. 69; Duvvury 1995; Ker, 1997]. These are deliberately drawn capacitors in addition to the parasitic capacitance already existing. At the initial stage of an ESD pulse, enough charge is coupled into the resistor such that it weakly turns on the NMOS device. By allowing the gate to tum on weakly, the snapback voltage is lowered, shown in Figure 2-13 as (VI;' It'd. If the snapback voltage is lowered sufficiently (VIl < Vd, then other fingers in an NMOS device will also snap back before anyone finger goes into a second breakdown.
The capacitor and resistor combination couples enough charge to help turn on the NMOS very weakly, ensuring lower snapback voltage (ViI) and allowing all the fingers to turn on. 32 ESD PROTECTION METHODOLOGY and is destroyed. If the second breakdown voltage Va is smaller than the snapback voltage VII, then the conducting finger will be destroyed even before other fingers snap back and share some ESD stress. This mechanism shows that if the drain is directly tied to the I/O pad, a finger that broke down earlier will continue to carry increasing amounts of current leading to its destruction.